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中文题名:

 高性能分段曲率补偿带隙基准电压源的设计    

姓名:

 李睿    

学号:

 13041023    

论文语种:

 chi    

学科名称:

 微电子学与固体电子学    

公开时间:

 公开    

学生类型:

 硕士    

学位:

 工学硕士    

学校:

 西南交通大学    

院系:

 信息科学与技术学院    

专业:

 微电子学与固体电子学    

第一导师姓名:

 冯全源    

第一导师单位:

 西南交通大学    

完成日期:

 2016-03-24    

答辩日期:

 2016-04-29    

外文题名:

 THE DESIGN OF HIGH PERFORMANCE PIECEWISE CURVATURE COMPENSATION BANDGAP VOLTAGE REFERENCE    

中文关键词:

 带隙基准 ; 分段曲率补偿 ; 温度系数 ; 电源抑制比    

外文关键词:

 Bandgap Reference ; Piecewise Curvature Compensation ; TC ; PSRR    

中文摘要:

基准源是DC/DC转换器、AC/DC转换器、充电保护芯片、LED驱动、线性稳压器、PWM调制器等常见的电源管理芯片中不可缺少的模块。它为电源管理芯片中的其他模块提供参考电压,基准源的精度、稳定性等性能将会直接影响到芯片的性能,因此设计高性能的基准源显得尤为重要。低电源电压、低温漂、高电源抑制比、低功耗是目前基准源研究的热点。带隙基准源是各种基准源架构中研究成熟使用广泛的一种基准拓扑结构。鉴于此,本文将对低温漂、高性能的带隙基准进行研究设计。
本文从双极型晶体管入手介绍了带隙基准电压的产生原理,分析了Kuijk、Widlar、Brokaw、Banba等几种传统的带隙基准结构。并研究了带隙电压的高阶温度特性,分析了几种常见的高阶温度补偿策略。在此基础上,设计了一种基于传统Kuijk带隙基准结构的高性能带隙基准。推导分析了电源抑制比与高性能运放之间的关系,设计了一种具有高增益和高电源抑制比的两级运放。给出了一种分段曲率补偿方案,通过利用CTAT电压和PTAT电压的温度特性以及MOS的亚阈值特性,在低温和高温时产生曲率补偿电压对基准电压进行了分段曲率补偿。
使用HSPICE仿真软件对带隙基准电路进行了仿真验证,所采用的工艺模型为UMC 0.25μm BCD。仿真结果表明温度在-40℃~125℃的范围内,补偿前的基准温度系数为13.7ppm/℃,补偿后的温度系数为2.8ppm/℃;低频时的电源抑制比为-91.2dB;线性调整率为24.57μV/V;基准环路的低频开环增益为64.6dB,相位裕度为83°;静态功耗电流为9.2μA。
从仿真结果看出,分段曲率补偿后的基准电压温度系数明显降低。此外,在电源抑制比、线性调整率、功耗等方面,本文所提出的带隙基准电路都具有一定的优势。

外文摘要:

In recent years, with the fast iterative development of the smart TV, smartphone, swearable devices, laptops and other consumer electronics, the performance requirements of chip increases gradually. Power managerment chip supply high stability and high efficiency of electricity for other chips in the circuit system. It’s indispensability for the circuit system. Reference source is the indispensable function module of power management chip such as DC/DC converter, AC/DC converter, charging protection chip, LED Circuit, linear voltage regulator, PWM modulator. It provides reference voltage for other function modules in a system. So, the precision, stability and other performance of reference source will directly affect the performance of the chip. So the design of high performance reference source is particularly important. Low supply voltage, low temperature drift, high power supply rejection ratio, low power consumption are the current hot research topics of reference source. Bandgap reference source is the most mature and widely used topological structure of reference source. Therefore, this article will study the low temperature drift and high performance bandgap voltage reference. 
Starting with the bipolar transister, this paper introduces the principle of bandgap voltage reference. And this paper analyzes the Kuijk, Widlar, Brokaw and Banba conventional bandgap reference structure. Then the higher-order temperature characteristic and commonly used higher-order temperature compensation methods are studied. On the basis of the above, this paper proposes and designs a high performance bandgap reference which is based on the traditional Kuijk bandgap reference structure. The relationship between the bandgap reference power supply rejection ratio(PSRR) and the high-performance op-amp is studied. Then a dual-stage amplifier with high gain and high PSRR is designed. A piecewise curvature compensation method is proposed. The temperature characteristic of CTAT and PTAT voltage, and the sub-threshold characteristic of MOS are used to make curvature compensation for bandgap reference voltage at the low and high temperature. 
Based on the UMC 0.25μm BCD process model and HSPICE simulation bench, the bandgap reference circuit is verified by simulation. The simulation result shows that uncompensated temperature coefficient(TC) of reference voltage is 13.7ppm/℃ at -40℃~125℃, and the TC after compensation is 2.8ppm/℃. The PSRR is -91.2dB at low frequency. The line regulation(LNR) is 24.57μV/V. The low frequency loop gain is 64.6dB, and the phase margin is 83 degrees. The quiescent power dissipation current is 9.2μA.
See from the simulation results, the TC obviously decrease after the reference voltage is compensated. In addition, the bandgap reference circuit in this paper has advantage on the performance of PSRR, LNR, power consumption, etc.

分类号:

 TN431.1    

总页码:

 77    

参考文献总数:

 62    

参考文献:

[1] 李珂. 中国集成电路产业步入加速发展期[J]. 电子工业专用设备, 2015(3): 6-9.

[2] 蔡凌. 2015年消费电子产品市场五大趋势预测[J]. 通信世界, 2015(3): 12-12.

[3] Shi C, Walker B, Zeisel E, et al. A Highly Integrated Power Management IC for Advanced Mobile Applications[J]. IEEE Journal of Solid-State Circuits, 2007, 42(8): 1723-1731.

[4] 刘欣. 电源管理芯片的分析与设计[D]. 吉林大学, 2009.

[5] 陈跃. 高效降压型DC/DC电源管理芯片XD1129的设计与实现[D]. 西安电子科技大学, 2012.

[6] Kuczynska M, Gozdur S, Bugiel S, et al. Development of radiation-hard bandgap reference and temperature sensor in CMOS 130 nm technology[C]. Mixed Design of Integrated Circuits & Systems. IEEE, 2015: 324-329

[7] 吴文兰, 刑立东. 带隙基准源的现状及其发展趋势[J]. 微计算机信息, 2010, 26(17): 186-188.

[8] 幸新鹏, 李冬梅, 王志华. CMOS带隙基准源研究现状[J]. 微电子学, 2008, 38(1): 57-63.

[9] 马克·皮尔森, 金国峰. 电压基准源的合理选择[J]. 电测与仪表, 2001, 38(04): 52-53.

[10] Mancini R. Designing a zener-diode regulator[J]. EDN, 2004, 49(16): 24-24.

[11] 瞿美霞. CMOS带隙基准源的研究与实现[D]. 合肥工业大学, 2007.

[12] Mancini R. The ultimate zener-diode reference[J]. EDN, 2004, 49(20): 26-26.

[13] 郭凌. 新型XFET基准电压源ADR290/291/292/293[J]. 电子设计工程, 2000(3): 43-43.

[14] Widlar R. New developments in IC voltage regulators[C]. Solid-State Circuits Conference. Digest of Technical Papers. IEEE, 1970: 158-159.

[15] Jiang Y, Lee E K F. Design of low-voltage bandgap reference using transimpedance amplifier[J]. Circuits & Systems II Analog & Digital Signal Processing IEEE Transactions on, 2000, 47(6): 552-555.

[16] Annema A J. Low-power bandgap references featuring DTMOSTs[J]. IEEE Journal of Solid-State Circuits, 1999, 34(7): 949 - 955.

[17] Miller S, Maceachern L. A nanowatt bandgap voltage reference for ultra-low power applications[C]. IEEE International Symposium on Circuits and Systems, 2006: 645-648.

[18] Lv J, Wei L, Ang S S. A new curvature-compensated, high-PSRR CMOS bandgap reference[J]. Analog Integrated Circuits & Signal Processing, 2015, 82: 1-8.

[19] Ming X, Ma Y Q, Zhou Z K, et al. A 1.3 ppm/°C BiCMOS bandgap voltage reference using piecewise-exponential compensation technique[J]. Analog Integrated Circuits & Signal Processing, 2011, 66(2): 171-176.

[20] 李景虎, 张兴宝, 周斌,等. 高阶分段非线性曲率校正带隙基准源[J]. 华中科技大学学报: 自然科学版, 2013, 41(8): 20-23.

[21] Mehrmanesh S, Vahidfar M B, Aslanzadeh H A, et al. A 1-volt, high PSRR, CMOS bandgap voltage reference[C]. International Symposium on Circuits and Systems. IEEE, 2003: 381-384.

[22] 刘春娟, 张帆, 王永顺,等. 高电源抑制比低噪声带隙基准电压源的设计[J]. 微电子学, 2012, 42(4): 527-530.

[23] Li W, Yao R, Guo L. A low power CMOS bandgap voltage reference with enhanced power supply rejection[C]. International Conference on Asic. IEEE, 2009: 300-304.

[24] 朱莎莎. 低压低功耗带隙基准电压源的设计[D]. 北京大学, 2012.

[25] Khot P, Shettar R B. Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors[C]. International Symposium on Vlsi Design and Test. IEEE, 2015.

[26] Ahuja B K, Vu H, Laber C, et al. A very high precision 500-nA CMOS floating-gate analog voltage reference[J]. IEEE Journal of Solid-State Circuits, 2006, 40(12): 2364-2372.

[27] 魏廷存. 模拟CMOS集成电路设计[M]. 清华大学出版社, 2010.

[28] Gray P R, Meyer R G. Analysis and Design of Analog Integrated Circuits[M]. John Wiley & Sons, Inc., 2001: 9-20.

[29] Filanovsky I M, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits[J]. Circuits & Systems I Fundamental Theory & Applications IEEE Transactions on, 2001, 48(7): 876-884.

[30] Behzad Razavi著, 陈贵灿等译. 模拟CMOS集成电路设计[M]. 西安交通大学出版社, 2002.

[31] Hilbiber D. A new semiconductor voltage standard[C]. Solid-state Circuits Conference Digest of Technical Papers IEEE International. IEEE, 1964: 32-33.

[32] 贺炜. 高精度曲率校正带隙基准电压源的设计[D]. 西南交通大学, 2015.

[33] Kuijk K E. A precision reference voltage source[J]. Solid-State Circuits, IEEE Journal of, 1973, 8(3): 222-226.

[34] Brokaw P. A simple three-terminal IC bandgap reference[J]. IEEE Journal of Solid-State Circuits, 1974, 9(6): 188-189.

[35] Banba H, Shiga H, Umezawa A, et al. A CMOS bandgap reference circuit with sub-1-V operation[J]. Solid-State Circuits, IEEE Journal of, 1999, 34(5): 670-674.

[36] 周洋. 高性能BiCMOS带隙基准电压源设计[D]. 江苏大学, 2010.

[37] Vishal Gupta. An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC[D]. Georgia Institute of Technology, 2007.

[38] 樊吉涛. 低失调低温漂运算放大器设计[D]. 哈尔滨理工大学, 2013.

[39] 朱波. 带数字自校正的CMOS带隙基准电压源设计[D], 电子科技大学, 2013.

[40] 吴春瑜, 李德第, 付强,等. 基于斩波调制的带隙基准电压源的设计[J]. 半导体技术, 2009, 34(5): 408-410.

[41] 金善子. 模拟电路版图设计中的匹配艺术[J]. 中国集成电路, 2006, 15(12): 48-51.

[42] Tsividis Y P. Accurate analysis of temperature effects in I/SUB c/V/SUB BE/ characteristics with application to bandgap reference sources[J]. Solid-State Circuits, IEEE Journal of, 1980, 15(6): 1076-1084.

[43] Brugler J S. Silicon Transistor Biasing for Linear Collector Current Temperature Dependence[J]. IEEE Journal of Solid-State Circuits, 1967, 2(2): 57-58.

[44] 徐伟. 带曲率补偿的带隙基准及过温保护电路研究与设计[D]. 西南交通大学, 2009.

[45] Leung K N, Mok P K T, Leung C Y. A 2-V 23-μA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference[J]. Solid-State Circuits, IEEE Journal of, 2003, 38(3): 561-564.

[46] 王国瑞. 高性能带隙基准电压源的分析与设计[D]. 吉林大学, 2010.

[47] Malcovati P, Maloberti F, Fiocchi C, et al. Curvature-compensated BiCMOS bandgap with 1-V supply voltage[J]. IEEE Journal of Solid-State Circuits, 2001, 36(7): 1076-1081.

[48] 林少波. 高精度高电源电压抑制比CMOS带隙基准源设计[D]. 西安电子科技大学, 2012.

[49] 谢佳. 高性能带隙基准源的设计与实现[D]. 电子科技大学, 2008.

[50] Lee I, Kim G, Kim W. Exponential curvature-compensated BiCMOS bandgap references[J]. Solid-State Circuits, IEEE Journal of, 1994, 29(11): 1396-1403.

[51] 高榕. 高精度BiCMOS基准源温度补偿策略及电路实现[D]. 西安电子科技大学, 2011.

[52] 李帅. 低压低功耗CMOS基准源补偿策略及电路设计[D]. 西安电子科技大学, 2010.

[53] 李睿, 冯全源. 一种低功耗高精度带隙基准的设计[J]. 电子技术应用, 2015, 41(3): 51-54.

[54] Giustolisi G, Palumbo G. A detailed analysis of power-supply noise attenuation in bandgap voltage references[J]. Circuits & Systems I Fundamental Theory & Applications IEEE Transactions on, 2003, 50(2): 185-197.

[55] 张涛. 低电压高电源抑制比带隙基准电路设计[D]. 华中科技大学, 2008.

[56] 张龙, 冯全源, 王丹. 一种带曲率补偿的低功耗带隙基准源设计[J]. 电子元件与材料, 2014, 33(9): 58-61.

[57] 曾健平, 邹韦华, 易峰,等. 高电源抑制比带隙基准电压源的设计[J]. 半导体技术, 2007, 32(11): 984-987.

[58] 李沁莲, 陈向东, 王丽娜. 基于衬底运放的2阶温度补偿带隙基准电路[J]. 微电子学, 2011, 41(3): 332-335.

[59] 李宏杰, 冯全源. 一种二阶曲率补偿的低温漂高精度带隙基准设计[J]. 电子元件与材料, 2014, 33(12): 65-69.

[60] 陆华明. LDO设计与温漂校准研究[D]. 苏州大学, 2014.

[61] 胡滨. 低压带隙基准源的设计[D]. 西安电子科技大学, 2011.

[62] 温威. CMOS Pipeline ADC/带隙基准电压源的设计[D]. 湖南大学, 2014.

馆藏位置:

 TN431.1 S 2016    

开放日期:

 2016-05-09    

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